1. Field of the Invention
The present invention relates to an element for a solid-state imaging device, and more particularly to a structure, of an element isolation region, which solves a problem of the element being micromachined.
2. Description of the Background Art
In recent years, in the field of a solid-state imaging device, various techniques related to a structure of an amplified MOS image sensor have been proposed. It is advantageous that the amplified MOS image sensor consumes less power than a CCD image sensor. Furthermore, in the amplified MOS image sensor, it is also advantageous that a CMOS process is used for mounting both a sensor portion and a peripheral circuit thereof, thereby allowing the sensor portion and the peripheral circuit thereof to be easily integrated with each other.
Referring to FIGS. 4 and 5, an element for a solid-state imaging device, according to the conventional art, disclosed in Japanese Laid-Open Patent Publication No. 2000-150847 will be described. FIG. 4 is a plan view illustrating the element for the solid-state imaging device according to the conventional art. FIG. 4 shows a photoelectric conversion region and a signal read region, both of which are included in a pixel. FIG. 5 is a cross-sectional view illustrating the element for the solid-state imaging device along lines Y1-Y2 of FIG. 4.
As shown in FIG. 4, in the pixel, a signal accumulation region (photodiode) 102, a gate electrode 104 and a drain region 105 constitute a MOS transistor.
Furthermore, as shown in FIG. 5, the gate electrode 104 is provided on the P type well 101 with a gate oxide film 103 interposed therebetween. The drain region 105, made of an N type diffusion layer, is formed on a surface portion, of the P type well 101, on which the gate electrode 104 is formed. The signal accumulation region 102, made of the N type diffusion layer for converting light into electric charge and accumulating the converted electric charge, is formed in an interior of the P type well 101 which is formed in a semiconductor substrate (not shown) The drain region 105 is located on a side, of the gate electrode 104, opposite to that on which the signal accumulation region 102 is located.
A surface shield layer 106 is formed on the surface portion of the P type well 101. The surface shield layer 106 is located, such that at least a portion of the surface shield layer 106 is faced to the signal accumulation region 102 with the P type well 101 therebetween. The surface shield layer 106 is made of a P type diffusion layer.
An element isolation region 107 is provided on the surface portion of the P type well 101. The element isolation region 107 has an STI (shallow Trench Isolation) structure. The element isolation region 107 is operable to insulate the pixel from an adjacent pixel. Such an STI structure is formed by etching the P type well 101 to form a groove (trench), and then filling the groove with a silicon oxide 108.
In the element for the MOS type solid-state imaging device using the STI structure mentioned above, it is known that a crystal defect is generated in a vicinity of an interface between the element isolation region 107 and a peripheral portion thereof. Further, it is also known that when the element for the solid-state imaging device is thermally treated, a stress generated in the vicinity of the interface between the element isolation region 107 and the peripheral portion thereof is the largest among stresses generated in other areas of the element. Such a stress is caused by a difference between a thermal expansion coefficient of a material included in the element isolation region 107 (e.g., silicon oxide) and a thermal expansion coefficient of the P type well 101. Due to the crystal defect and the stress mentioned above, a leakage current flows from the element isolation region 107 into the signal accumulation region 102. When the leakage current flows into the signal accumulation region 102, a charge derived from the leakage current is added to a signal charge accumulated in the signal accumulation region 102, thereby causing white blemishes and minute unevenness to be generated on a screen when reproducing an image.
Nowadays, among the white blemishes and minute unevenness mentioned above, the white blemishes and minute unevenness caused by the crystal defect can be eliminated, by using an image correction technique developed along with the recent advancements in digital techniques, because the number of the white blemishes and minute unevenness caused by the crystal defect is relatively small. However, the stress is generated in almost all pixels. In other words, the stress is generated throughout an entirety of the screen. Thus, in order to eliminate, by using the image correction technique, the blemishes and minute unevenness caused by the stress, a memory having a large capacity is needed. As a result, it becomes difficult to miniaturize the imaging device, and to reduce electrical power consumed thereby, etc. Furthermore, steps and time required for fabricating the memory are caused to be increased, thereby resulting in an increased fabrication cost.
In order to solve the problems mentioned above, Japanese Laid-Open Patent Publication No. 2004-253729 proposes a technique, as shown in FIG. 6, in which a defect suppression layer 109, made of the P type diffusion layer, is provided along an entire exterior surface of the element isolation region 107. The defect suppression layer 109 is filled with a P type hole. By forming the defect suppression layer 109, it becomes possible to reduce the leakage current and a noise.
Furthermore, Japanese Laid-Open Patent Publication No. 2004-253729 discloses, as shown in FIG. 7, steps for forming the defect suppression layer 109. FIG. 7 is a schematic cross-sectional view illustrating steps, for implanting ions, performed when the defect suppression layer 109 is formed. As shown in FIG. 7, the P type well 101 is etched to form a groove (trench) 110. Thereafter, ions are implanted into an inner wall of the groove 110, thereby forming the defect suppression layer 109 along the entire exterior surface of the element isolation region 107. As shown by arrows in the FIG. 7, ions are implanted in diagonal directions with respect to the surface of the P type well 101.
However, the conventional art disclosed in Japanese Laid-Open Patent Publication No. 2004-253729 has the following problems. Specifically, along with the miniaturization of the element, a width of the groove 110, from which the element isolation region 107 is to be made, accordingly becomes narrower. In such a case, when ions are implanted in the diagonal directions with respect to the surface of the P type well 101, as shown in FIG. 8, there may be a case where the ions cannot be implanted directly into a surface of a deep portion of the groove 110. Therefore, the element for the solid-state imaging device, according to the conventional art, disclosed in Japanese Laid-Open Patent Publication No. 2004-253729, has a first problem in that there may be a case where the defect suppression layer 109 cannot be formed in an appropriate manner.
Furthermore, in the case where the defect suppression layer 109 is formed, as shown in FIG. 9, the defect suppression layer 109 causes a width of the signal accumulation region 102 to be reduced. Thus, a technique disclosed in Japanese Laid-Open Patent Publication No. 2004-253729 has a problem in that a capacity of the signal accumulation region 102 is caused be reduced when forming the defect suppression layer 109. Thus, a second problem of the element for the solid-state imaging device, according to the conventional art, is in that when a volume of the signal accumulation region 102 becomes reduced along with the miniaturization of the element, the capacity, of the signal accumulation region 102, which is reduced by forming the defect suppression layer 109, can be severe.